1. Field of the Invention
This disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a fabrication method that includes forming a bit-line with a damascene process after a storage node contact formation. This prevents bridge failures caused by voids and reduces a leakage current.
2. Description of the Related Art
Generally, as the size of a semiconductor memory device decreases, the cell pitch is correspondingly reduced. The reduction in pitch causes problems such as voids due to gap-fill failures in an inter-insulation layer, bridge failures between the storage node contacts due to the voids, and leakage current between the bit-line and the storage node contact due to scaling down the size of the bit-line spacer.
FIGS. 1A, 2A, 3A, and 4A are cross-sectional views and FIGS. 1B, 2B, 3B, and FIG. 4B are corresponding plan views illustrating a fabrication method of a conventional semiconductor memory device. FIGS. 1A and 2A are cross-sectional views taken along the line IA—IA of FIG. 4B, and FIGS. 3A and 4A are cross-sectional views illustrating the relation between a bit-line and a storage node contact of the prior semiconductor memory device having a plan structure of FIG. 4B.
Referring to FIGS. 1A and 1B, a silicon substrate 100 includes a field region 101 and an active region 105, and a conventional shallow trench isolation STI process is performed to form a field isolation region 110 in the field region 101 of the silicon substrate 100. Gates 120 crossing the active region 105 are formed on the silicon substrate 100. In other words, on the silicon substrate 100, a gate insulation layer 121, a polysilicon layer 123, a tungsten (W) layer 125, and a cap nitride layer 127 are deposited sequentially and patterned using a gate mask (not shown) to form the gates 120. Furthermore, a gate spacer 130, such as a nitride layer, is formed on the sidewall of each gate 120.
Referring to FIGS. 2A and 2B, a first inter-insulation layer 140 on the silicon substrate 100 and a conventional self-aligned contact process is performed to form self-aligned contacts (SACs) 150. A conductive layer for a SAC contact pad, for example a polysilicon layer, is deposited, and a chemical mechanical polishing (CMP) process or an etch-back process is performed to form SAC contact pads 160 in the SACs 150, respectively. Sequentially, a second inter-insulation layer 170 is deposited on the silicon substrate 100 and patterned to form a bit-line contact 175 to expose the corresponding contact pad of the SAC contact pads 160 which is to be connected with a bit-line in the following process.
Referring to FIGS. 3A and 3B, a conductive layer for a bit line and a capping insulation layer, such as a nitride layer, are deposited on the silicon substrate 100. The conduction layer and the capping insulation layer are patterned to form a bit-line 180 that includes a capping layer 185. The bit-line 180 is connected with the corresponding SAC contact pad 160 through the bit-line contact 175.
Referring to FIGS. 4A and 4B, a third inter-insulation layer 190 is deposited on the substrate 100 and the third inter-insulation layer 190 and the second inter-insulation layer 170 are patterned to form a storage node contact 195. The storage node contact 195 exposes the corresponding contact pad of the SAC contacts pads. Even though not shown in the drawings, a conventional capacitor fabrication process is performed to form a capacitor connected with the corresponding SAC contact pad 160 through the storage node contact 195, thereby fabricating a conventional dynamic random access memory (DRAM) device.
However, the conventional DRAM device fabrication method has the problems of reduction in a thickness of the bit-line spacer due to reduction in a cell pitch, and a leakage current between the bit-line 180 and the storage node contact 195 due to the thickness reduction of the bit-line spacer. In more, the conventional DRAM device fabrication method also has the problems of a void due to a gap-fill fail in the third inter-insulation layer 190, a bridge fail between the storage node contacts 195 due to the void, and a reduction of the overlay margin of the storage node contact 195.
Embodiments of the invention address these and other problems in the prior art.